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XILINX VIVADO IDE HOW TO
XILINX VIVADO IDE DRIVER
XILINX VIVADO IDE ARCHIVE

vivado_hls - Vivado HLS projects for image filters.The following files are inside the xapp1231-partial-reconfig-hw-accelerator-vivado top-level directory:

XILINX VIVADO IDE ARCHIVE

The pre-built bitstreams and boot images are built from a full logiCVC-ML IP core.ĭownload and unzip the reference design archive file xapp1231-partial-reconfig-hw-accelerator-vivado.zip to a local directory. The evaluation IP core has a 1 hour timeout built-in such that the display output freezes after the timer expires.

Xylon logiCVC-ML is provided as evaluation IP core that does not require a license.

Xilinx IP evaluation licenses may be provided with the Vivado Design Suite or can be ordered online.

Xilinx Partial Reconfiguration is a product inside the Vivado Design Suite that requires a license.

Avnet FMC-IMAGEON module and external video source that provides 1080p60 video input over HDMI (optional).

Monitor with HDMI or DVI port that supports 1080p60 video resolution.

Note: Some tools are optional and the corresponding design flow tutorials can be skipped.

Git distributed version control system (optional).

XILINX VIVADO IDE DRIVER

Silicon Labs CP210x USB to UART Bridge VCP Driver.

Vivado Design Suite 2014.4 System Edition, includes Vivado High-Level Synthesis (HLS).

XILINX VIVADO IDE HOW TO

The provided reference design demonstrates how to use software-controlled Partial Reconfiguration through the Processor Configuration Access Port (PCAP) to dynamically reconfigure part of the PL with the desired image filter IP core and observe the modified video output on a monitor. For this reference design, three image filter IP cores are generated using Vivado HLS: Posterize, Sobel, FAST. The image filter IP core demonstrated in the ZC702 Base TRD is a Sobel filter configured with edge detection coefficients which has been generated using Vivado HLS. In this example a compute-intensive video filtering algorithm is moved from the Processing System (PS) onto a hardware accelerator in Programmable Logic (PL). The PR reference design is built on top of the ZC702 Base Targeted Reference Design (TRD), an embedded video processing application that demonstrates how it is best to separate control and data processing functions. ISE 14.4 XAPP1159 - Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 SoC Devices 1.1 Design Overview The previous versions of this reference design is available at the links below: It complements application note XAPP1231 which focuses on conceptual aspects of the PR flow and design considerations specific to the Zynq architecture. This tutorial shows how to develop a Partial Reconfiguration (PR) design for the Zynq-7000 SoC using the Xilinx Vivado Design Suite, Vivado HLS, Software Development Kit (XSDK), and PetaLinux design tools.